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Logic x project latency free.Create an integration workflow with single-tenant Azure Logic Apps (Standard) in Visual Studio Code

 

I was initially going to look at real numbers in this part, but Project F is known for its practical, hands-on tutorials. So, I decided to dedicate a post to a topic usually ignored by introductory guides: multiplication with DSPs. This post was last updated in December I love FPGAs and want to help more people discover and use them in their projects. My hardware designs are open source, and my blog is advert free. Just bear in mind that DSP blocks are useful for many things beyond straight multiplication.

You can also implement multiplication directly in logic LUTs and flip-flops , but it takes significant resources. Using dedicated DSP blocks for multiplication makes sense from a performance and logic-use perspective. Vendor primitives allow you to fine-tune your implementation but are more complex and limit your design to a single FPGA architecture.

I also provide Verilator simulations of the designs. Our examples run mathematical functions for each pixel on the screen, generating a 0 or 1 as output. The function needs to keep pace with the display signal: calculating 25 million values per second for x or 74 million for x This module takes the X and Y coordinates of a pixel and returns 1 if X squared is larger than the scaled Y value explained below.

When we square X, the value quickly becomes too large to fit on screen if we assume each vertical pixel represents 1. To make more of the function visible, we scale the Y-axis with a parameter. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. This adds an additional cycle of latency, so we need to delay the Y value:.

Built with Vivado The extra pipeline stage uses a little more logic and adds an additional cycle of latency. Timing on the XC7AT is actually worse for our pipelined design, but still comfortable.

The larger this number, the better, but you need to account for the target clock speed. Again, we create two versions and compare them. At 74 MHz there is some improvement, but both versions have generous slack considering the target frequency.

In the initial version of cubed, we have two multiplications in one expression. Interestingly, if the signal width is 16, it requires three DSPs, while bit signals need only two. This is another reason to infer DSPs for multiplication: synthesis tools can make non-obvious optimisations.

However, the number of flip flops goes down in the pipelined version. The 74 MHz results mirror 25 MHz, though timing is starting to get tight for the non-pipelined design. For 74 MHz, the complexity has caught up with us, and v1 misses timing by quite a margin.

However, the pipelined version is still comfortable. Notably, the extra pipeline stages also halve the number of DSPs required from 6 to 3. Implementing an algorithm in hardware is always a balancing act, never more so than when using DSPs. Adding pipeline stages and registering outputs is almost always worthwhile, but it does increase latency, which is problematic for some applications.

Using narrower signals saves logic but reduces accuracy or range. Welcome back to my series covering mathematics and algorithms with FPGAs. New to the series? Start with Numbers in Verilog.